1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of bipolar transistors.
2. Background Art
As modern electronic devices increase in speed while decreasing in size and price, semiconductor manufacturers are challenged to provide low-cost, high speed, and small size transistors for these devices. To meet this challenge, semiconductor manufacturers must accurately control the size of certain features that critically affect the performance of transistors on a semiconductor wafer, such as emitter widths of bipolar transistors. Furthermore, various parts of the bipolar transistor must be properly aligned to ensure that the bipolar transistor meets performance requirements. For example, the emitter and the extrinsic base implant in a heterojunction bipolar transistor (HBT) must be properly aligned to prevent an undesirable increase in base resistance.
In one conventional fabrication process for a bipolar transistor, such as an HBT, semiconductor manufacturers utilize a first photomask to control the bipolar transistor""s emitter width, which is generally referred to as a critical dimension, or xe2x80x9cCD.xe2x80x9d A second photomask, which must be properly aligned with the first photomask, is utilized to determine the boundaries of the heavily doped extrinsic base regions of the bipolar transistor. Misalignment of the two photomasks causes, among other things, the distance across the link base region of the bipolar transistor, i.e. the region between the base-emitter junction and the extrinsic base region, to vary in an unpredictable fashion. Since there need be a margin for error in the alignment of the two photomasks, the distance across the link base region must be increased to account for such misalignment. This results, for example, in an undesirable increase in base resistance. Additionally, in the two-photomask fabrication process described above, the first photomask must be accurately controlled to control the emitter width of the bipolar transistor. Also, misalignment of the two photomasks can cause an undesirable reduction in manufacturing yield, which can cause a corresponding increase in manufacturing cost.
Other fabrication processes and tools have been tried in attempts to solve the problem of aligning the link base and extrinsic base to the emitter in bipolar transistor devices. One approach requires the use of selective epitaxy along with the use of an inside spacer. Selective epitaxy presents a problem in that it is not currently used in high volume production of semiconductor devices. Selective epitaxy presents another problem in that selective epitaxial deposition occurs only on silicon regions and not on oxide regions. Since most process monitoring is done on oxide regions, selective epitaxy results in a substantial loss of process monitoring capability. Use of an inside spacer presents a further problem in that variability of emitter width is greater than with other methods, so some accuracy in control of emitter width is lost.
In addition, as feature sizes of bipolar devices are reduced, it is important and more difficult to achieve accurate control over the size of certain features, such as the emitter width of the bipolar transistor.
Thus, there is need in the art for a fabrication process for bipolar transistors which does not rely on the alignment of separate photomasks to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region.
The present invention is directed to method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure. The present invention addresses and resolves the need in the art for a fabrication process for bipolar transistors which does not rely on the alignment of separate photomasks to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region of the bipolar transistor.
According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a first link spacer and a second link spacer situated on the top surface of the base. The bipolar transistor further comprises a sacrificial post situated on the top surface of the base between the first link spacer and the second link spacer. The first and second link spacers may have a height, for example, approximately equal to or, in another embodiment, substantially less than a height of the sacrificial post.
According to this exemplary embodiment, the bipolar transistor further comprises a non-sacrificial planarizing layer situated over the sacrificial post, the first and second link spacers, and the base. The non-sacrificial planarizing layer may comprise, for example, silicate glass. The sacrificial planarizing layer may have a height, for example, that is approximately equal to or, in another embodiment, greater than a height of the first and second link spacers. The bipolar transistor may further comprise a mask situated over the non-sacrificial planarizing layer, where the mask has an emitter window opening. In another embodiment, the present invention is a method that achieves the above-described bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.